A built-in self-repair scheme for multiport RAMs

Tsu Wei Tseng, Chun Hsien Wu, Yu Jen Huang, Jin Fu Li, Alex Pao, Kevin Chiu, Eliot Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

22 Scopus citations

Abstract

Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 × 128-bit MPRAM with 1 spare row and 1 spare IO.

Original languageEnglish
Title of host publicationProceedings - 25th IEEE VLSI Test Symposium, VTS'07
Pages355-360
Number of pages6
DOIs
StatePublished - 2007
Event25th IEEE VLSI Test Symposium, VTS'07 - Berkeley, CA, United States
Duration: 6 May 200710 May 2007

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference25th IEEE VLSI Test Symposium, VTS'07
Country/TerritoryUnited States
CityBerkeley, CA
Period6/05/0710/05/07

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