A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih Sheng Hou, Yong Xiao Chen, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE International Test Conference, ITC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467387736
DOIs
StatePublished - 2 Jul 2016
Event47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States
Duration: 15 Nov 201617 Nov 2016

Publication series

NameProceedings - International Test Conference
Volume0
ISSN (Print)1089-3539

Conference

Conference47th IEEE International Test Conference, ITC 2016
Country/TerritoryUnited States
CityFort Worth
Period15/11/1617/11/16

Keywords

  • built-in self-repair
  • built-in self-Test
  • DRAM
  • redundancy
  • redundancy analysis

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