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With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.
|Title of host publication||Proceedings - 2016 IEEE International Test Conference, ITC 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - 2 Jul 2016|
|Event||47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States|
Duration: 15 Nov 2016 → 17 Nov 2016
|Name||Proceedings - International Test Conference|
|Conference||47th IEEE International Test Conference, ITC 2016|
|Period||15/11/16 → 17/11/16|
- built-in self-repair
- built-in self-Test
- redundancy analysis
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1/05/15 → 31/07/16