A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih Sheng Hou; Yong Xiao Chen; Jin Fu Li; Chih Yen Lo; Ding Ming Kwai; Yung Fa Chou

doi:10.1109/TEST.2016.7805832

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih Sheng Hou, Yong Xiao Chen, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

Original language	English
Title of host publication	Proceedings - 2016 IEEE International Test Conference, ITC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467387736
DOIs	https://doi.org/10.1109/TEST.2016.7805832
State	Published - 2 Jul 2016
Event	47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States Duration: 15 Nov 2016 → 17 Nov 2016

Publication series

Name	Proceedings - International Test Conference
Volume	0
ISSN (Print)	1089-3539

Conference

Conference	47th IEEE International Test Conference, ITC 2016
Country/Territory	United States
City	Fort Worth
Period	15/11/16 → 17/11/16

Keywords

DRAM
built-in self-Test
built-in self-repair
redundancy
redundancy analysis

Access to Document

10.1109/TEST.2016.7805832

應用於三維積體電路可測性及可靠性設計技術-總計畫暨子計畫一：三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術
Li, J.-F. (PI)
1/05/15 → 31/07/16
Project: Research

Cite this

Hou, C. S., Chen, Y. X., Li, J. F., Lo, C. Y., Kwai, D. M., & Chou, Y. F. (2016). A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. In Proceedings - 2016 IEEE International Test Conference, ITC 2016 Article 7805832 (Proceedings - International Test Conference; Vol. 0). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2016.7805832

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abstract = "With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.",

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Hou, CS, Chen, YX, Li, JF, Lo, CY, Kwai, DM & Chou, YF 2016, A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. in Proceedings - 2016 IEEE International Test Conference, ITC 2016., 7805832, Proceedings - International Test Conference, vol. 0, Institute of Electrical and Electronics Engineers Inc., 47th IEEE International Test Conference, ITC 2016, Fort Worth, United States, 15/11/16. https://doi.org/10.1109/TEST.2016.7805832

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. / Hou, Chih Sheng; Chen, Yong Xiao; Li, Jin Fu et al.
Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7805832 (Proceedings - International Test Conference; Vol. 0).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chen, Yong Xiao

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AU - Kwai, Ding Ming

AU - Chou, Yung Fa

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AB - With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

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A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

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應用於三維積體電路可測性及可靠性設計技術-總計畫暨子計畫一：三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術

Cite this