A built-in self-repair scheme for 3-D RAMs with interdie redundancy

Che Wei Chou, Yu Jen Huang, Jin Fu Li

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

Original languageEnglish
Article number6480861
Pages (from-to)572-583
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume32
Issue number4
DOIs
StatePublished - 2013

Keywords

  • 3-D integrated circuit (IC)
  • 3-D random access memory (RAM)
  • memory repair
  • memory testing
  • through-silicon-via (TSV)
  • yield improvement

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