A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy

Yu Jen Huang, Da Ming Chang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

With the increasing demand of memories in system-on-chip (SOC) designs, developing efficient yield-improvement techniques for memories becomes an important issue. Built-in self-repair (BISR) technique has become a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) function is usually needed for designing a BISR scheme. This paper presents an efficient BIRA scheme for RAMs with two-level redundancy (i.e., spare rows, spare columns, and spare words). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the exhaustive search with the same redundancy organization. Furthermore, the repair rate of the proposed BIRA scheme with two-level redundancy is higher than that of the exhaustive search scheme with one-level redundancy (i.e., spare rows and spare columns). The area cost of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA scheme for an 8K×64-bit RAM with three spare rows, three spare columns, and two spare words is only about 2%.

Original languageEnglish
Title of host publicationProceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06
Pages362-370
Number of pages9
DOIs
StatePublished - 2006
Event2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, United States
Duration: 4 Oct 20066 Oct 2006

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Country/TerritoryUnited States
CityArlington, VA
Period4/10/066/10/06

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