A built-in redundancy-analysis scheme for RAMs with 3D redundancy

Yi Ju Chang, Yu Jen Huang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Built-in self-repair (BISR) techniques have been widely used to enhance the yield of embedded memories. Built-in redundancy-analysis (BIRA) module is one key component of the BISR circuit. In this paper, we present a BIRA scheme for random access memories (RAMs) with 3D redundancy to improve the yield of RAMs with cluster faults. A RAM with 3D redundancy is equipped with spare rows, spare columns, and spare IOs. The proposed BIRA scheme also can be designed as programmable such that it can serve multiple RAMs and support the multiple-time repair to increase the repair rate further. Experimental results show that the proposed BISR scheme can achieve high repair rate and only incurs 0.4% additional area overhead, compared with an existing BIRA scheme.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages264-267
Number of pages4
DOIs
StatePublished - 2011
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
Duration: 25 Apr 201128 Apr 2011

Publication series

NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country/TerritoryTaiwan
CityHsinchu
Period25/04/1128/04/11

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