A built-in redundancy-analysis scheme for RAMs with 2D redundancy using ID local bitmap

Tsu Wei Tseng, Jin Fu Li, Da Ming Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Scopus citations

Abstract

Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-on-chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform built-in redundancy-analysis (BIRA) algorithm for redundancy allocation. This paper presents an effcient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy allocation based on the ID local bitmap. This enables that the BIRA circuitry can be implemented with low area cost. Also, the BIRA algorithm can provide good repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the optimal scheme for the memories with different fault distributions. Also, the ratio of the analysis time to the test time is small.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE'06
StatePublished - 2006
EventDesign, Automation and Test in Europe, DATE'06 - Munich, Germany
Duration: 6 Mar 200610 Mar 2006

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume1
ISSN (Print)1530-1591

Conference

ConferenceDesign, Automation and Test in Europe, DATE'06
Country/TerritoryGermany
CityMunich
Period6/03/0610/03/06

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