Abstract
Several researchers proposed a shared parallel built-in self-repair (BISR) scheme for RAMs in SoCs to reduce test-and-repair time. They also described an automation framework for planning and generating parallel BISR circuits for RAMs in a SoC. The proposed shared parallel BISR scheme reduced area cost and needed the approximate test-and-repair time of the dedicated parallel BISR scheme. The parallel BISR design contained N wrappers and a central control-and-analysis (CCA) unit. The wrapper consisted of a test pattern generator (TPG), a local bitmap, and a simple controller for performing two redundancy analysis rules and interacting with the CCA unit. The TPG generated test patterns according to the test command sent from the CCA unit, while the local bitmap collected the faulty information of the faults detected by the TPG.
Original language | English |
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Article number | 5648494 |
Pages (from-to) | 46-57 |
Number of pages | 12 |
Journal | IEEE Design and Test of Computers |
Volume | 27 |
Issue number | 6 |
DOIs | |
State | Published - Nov 2010 |
Keywords
- SoC
- built-in self-repair
- design and test
- embedded memories
- redundancy analysis
- yield improvement