A built-in method for measuring the delay of TSVs in 3D ICs

Han Yu Wu, Yong Xiao Chen, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a built-in delay measurement (BIDM) technique to measure the delay of through-silicon via (TSV) in the phase of post-bond test. The BIDM circuit can be shared by multiple TSVs such that the area overhead of the BIDM circuit is minimized. Furthermore, a measurement flow is proposed to eliminate the delay of interconnection between two TSVs such that the BIDM accuracy is not worsened with the increased number of measured TSVs. Experimental results show that the deviation of the result of BIDM and Hspice simulation is about 2.7%. Furthermore, a low-cost delay measurement element is proposed. In comparison with a typical Vernier delay line, the proposed delay measurement element can achieve 18% area reduction. In comparison with the ring-oscillator-based delay measurement method, the proposed BIDM has the features of low error and low cost, but needs long measurement time.

Original languageEnglish
Title of host publicationProceedings - 2016 21st IEEE European Test Symposium, ETS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467396592
DOIs
StatePublished - 22 Jul 2016
Event21st IEEE European Test Symposium, ETS 2016 - Amsterdam, Netherlands
Duration: 23 May 201626 May 2016

Publication series

NameProceedings of the European Test Workshop
Volume2016-July
ISSN (Print)1530-1877
ISSN (Electronic)1558-1780

Conference

Conference21st IEEE European Test Symposium, ETS 2016
Country/TerritoryNetherlands
CityAmsterdam
Period23/05/1626/05/16

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