A block-based architecture for lifting scheme discrete wavelet transform

Chung Hsien Yang, Jia Ching Wang, Jhing Fa Wang, Chi Wei Chang

Research output: Contribution to journalArticlepeer-review

19 Scopus citations

Abstract

Two-dimensional discrete wavelet transform (DWT) for processing image is conventionally designed by line-based architectures, which are simple and have low complexity. However, they suffer from two main shortcomings - the memory required for storing intermediate data and the long latency of computing wavelet coefficients. This work presents a new block-based architecture for computing lifting-based 2-D DWT coefficients. This architecture yields a significantly lower buffer size. Additionally, the latency is reduced from N2 down to 3N as compared to the line-based architectures. The proposed architecture supports the JPEG2000 default filters and has been realized in ARM-based ALTERA EPXA10 Development Board at a frequency of 44.33 MHz.

Original languageEnglish
Pages (from-to)1062-1071
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE90-A
Issue number5
DOIs
StatePublished - May 2007

Keywords

  • Discrete wavelet transform
  • JPEG2000
  • Lifting scheme
  • Linebased DWT
  • VLSI

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