Abstract
Two-dimensional discrete wavelet transform (DWT) for processing image is conventionally designed by line-based architectures, which are simple and have low complexity. However, they suffer from two main shortcomings - the memory required for storing intermediate data and the long latency of computing wavelet coefficients. This work presents a new block-based architecture for computing lifting-based 2-D DWT coefficients. This architecture yields a significantly lower buffer size. Additionally, the latency is reduced from N2 down to 3N as compared to the line-based architectures. The proposed architecture supports the JPEG2000 default filters and has been realized in ARM-based ALTERA EPXA10 Development Board at a frequency of 44.33 MHz.
Original language | English |
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Pages (from-to) | 1062-1071 |
Number of pages | 10 |
Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Volume | E90-A |
Issue number | 5 |
DOIs | |
State | Published - May 2007 |
Keywords
- Discrete wavelet transform
- JPEG2000
- Lifting scheme
- Linebased DWT
- VLSI