A 64-MHz∼640-MHz 64-phase clock generator

Hong Yi Huang, Jen Chieh Liu, Shi Jia Sun, Cheng Hao Fu, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um2. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.

Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
EditorsSerge Bernard, Witold Pleskacz, Dominik Kasprowicz, Lukas Sekanina, Michel Renovell
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages51-54
Number of pages4
ISBN (Electronic)9781479945580
DOIs
StatePublished - 30 Jul 2014
Event17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 - Warsaw, Poland
Duration: 23 Apr 201425 Apr 2014

Publication series

NameProceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014

Conference

Conference17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
Country/TerritoryPoland
CityWarsaw
Period23/04/1425/04/14

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