A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-μm CMOS technology

Bo Qian Jiang, Cheng Liang Hung, Bing Hung Chen, Kuo Hsing Cheng

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only one clock instead of the multi-phase clock, and the complexity of the clock distribution network could be mitigated than counterpart. The study has been implemented in TSMC 0.13 um. Operating at the 6-Gb/s data rate and 3-GHz clock frequency, the estimated peak to peak jitter of the recovered clock is 7.55 ps, and the recovered data jitter is less than 6.4 ps. The core area of data recovery (DR) loop occupies 0.291 mm 2. The core power consumption of the all loops including I/O buffer is around 50 mW at the supply voltage of 1.2V.

Original languageEnglish
Pages2597-2600
Number of pages4
DOIs
StatePublished - 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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