A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme

Shyh Shyuan Sheu; Pei Chia Chiang; Wen Pin Lin; Heng Yuan Lee; Pang Shiu Chen; Yu Sheng Chen; Tai Yuan Wu; Frederick T. Chen; Keng Li Su; Ming Jer Kao; Kuo Hsing Cheng; Ming Jinn Tsai

A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme

Shyh Shyuan Sheu, Pei Chia Chiang, Wen Pin Lin, Heng Yuan Lee, Pang Shiu Chen, Yu Sheng Chen, Tai Yuan Wu, Frederick T. Chen, Keng Li Su, Ming Jer Kao, Kuo Hsing Cheng, Ming Jinn Tsai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

113 Scopus citations

Abstract

A 1-Kb HfO2 based RRAM for high speed nonvolatile memory application is proposed. With this chip, a high speed write characteristic in the RRAM cell can be achieved. The present circuit design includes a 1T1R RRAM (1 transistor/1 resistive memory) cell and a voltage write circuit, which limit the current through the memory cell. The random write time at VDD = 3.3V is as fast as 5 ns in the RRAM, which were fabricated with a 0.18 m TSMC process.

Original language	English
Title of host publication	2009 Symposium on VLSI Circuits
Pages	82-83
Number of pages	2
State	Published - 2009
Event	2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 16 Jun 2009 → 18 Jun 2009

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2009 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	16/06/09 → 18/06/09

Cite this

Sheu, S. S., Chiang, P. C., Lin, W. P., Lee, H. Y., Chen, P. S., Chen, Y. S., Wu, T. Y., Chen, F. T., Su, K. L., Kao, M. J., Cheng, K. H., & Tsai, M. J. (2009). A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. In 2009 Symposium on VLSI Circuits (pp. 82-83). Article 5205283 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{6eb0db16c01d4cac8192135a2108ef5a,

title = "A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme",

abstract = "A 1-Kb HfO2 based RRAM for high speed nonvolatile memory application is proposed. With this chip, a high speed write characteristic in the RRAM cell can be achieved. The present circuit design includes a 1T1R RRAM (1 transistor/1 resistive memory) cell and a voltage write circuit, which limit the current through the memory cell. The random write time at VDD = 3.3V is as fast as 5 ns in the RRAM, which were fabricated with a 0.18 m TSMC process.",

author = "Sheu, \{Shyh Shyuan\} and Chiang, \{Pei Chia\} and Lin, \{Wen Pin\} and Lee, \{Heng Yuan\} and Chen, \{Pang Shiu\} and Chen, \{Yu Sheng\} and Wu, \{Tai Yuan\} and Chen, \{Frederick T.\} and Su, \{Keng Li\} and Kao, \{Ming Jer\} and Cheng, \{Kuo Hsing\} and Tsai, \{Ming Jinn\}",

year = "2009",

language = "???core.languages.en\_GB???",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "82--83",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

}

Sheu, SS, Chiang, PC, Lin, WP, Lee, HY, Chen, PS, Chen, YS, Wu, TY, Chen, FT, Su, KL, Kao, MJ, Cheng, KH & Tsai, MJ 2009, A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. in 2009 Symposium on VLSI Circuits., 5205283, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 82-83, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 16/06/09.

A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. / Sheu, Shyh Shyuan; Chiang, Pei Chia; Lin, Wen Pin et al.
2009 Symposium on VLSI Circuits. 2009. p. 82-83 5205283 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme

AU - Sheu, Shyh Shyuan

AU - Chiang, Pei Chia

AU - Lin, Wen Pin

AU - Lee, Heng Yuan

AU - Chen, Pang Shiu

AU - Chen, Yu Sheng

AU - Wu, Tai Yuan

AU - Chen, Frederick T.

AU - Su, Keng Li

AU - Kao, Ming Jer

AU - Cheng, Kuo Hsing

AU - Tsai, Ming Jinn

PY - 2009

Y1 - 2009

N2 - A 1-Kb HfO2 based RRAM for high speed nonvolatile memory application is proposed. With this chip, a high speed write characteristic in the RRAM cell can be achieved. The present circuit design includes a 1T1R RRAM (1 transistor/1 resistive memory) cell and a voltage write circuit, which limit the current through the memory cell. The random write time at VDD = 3.3V is as fast as 5 ns in the RRAM, which were fabricated with a 0.18 m TSMC process.

AB - A 1-Kb HfO2 based RRAM for high speed nonvolatile memory application is proposed. With this chip, a high speed write characteristic in the RRAM cell can be achieved. The present circuit design includes a 1T1R RRAM (1 transistor/1 resistive memory) cell and a voltage write circuit, which limit the current through the memory cell. The random write time at VDD = 3.3V is as fast as 5 ns in the RRAM, which were fabricated with a 0.18 m TSMC process.

UR - http://www.scopus.com/inward/record.url?scp=70449393681&partnerID=8YFLogxK

M3 - 會議論文篇章

AN - SCOPUS:70449393681

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 82

EP - 83

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -

A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme

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