A 5.8-GHz power amplifier with an on-chip tunable output matching network

Yi Chun Lee, Jia Shiang Fu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


The power efficiency of power amplifiers (PAs) at low drive levels can be enhanced if the load impedance presented to the transistors can be adjusted using a tunable output matching network. In this work, a 5.8-GHz PA with an on-chip tunable output matching network on a GaAs 0.15-m pHEMT process is presented. As opposed to most of the previous work in the literature, the varactor-based continuously tunable matching network presented here is fully-integrated. Moreover, in this work, another PA with a fixed output matching network is fabricated on the same chip with the tunable PA for the purpose of comparison. The measured saturation power levels for both PAs are 22.2 dBm. At the output power level of 17.5 dBm, a 4% PAE improvement is observed. This translates into a 16% reduction in DC power consumption.

Original languageEnglish
Title of host publicationAsia-Pacific Microwave Conference Proceedings, APMC 2011
Number of pages4
StatePublished - 2011
EventAsia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia
Duration: 5 Dec 20118 Dec 2011

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC


ConferenceAsia-Pacific Microwave Conference, APMC 2011
CityMelbourne, VIC


  • Efficiency
  • power amplifiers
  • tunable matching networks


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