@inproceedings{3e38bc5086f74a578cf0c212e49bce60,
title = "A 538Mbps 2×64 spatial permutation modulation detector for MIMO systems",
abstract = "Spatial permutation modulation (SPM) is a new multiple-input-multiple-output (MIMO) technology for next-generation communication systems, which is an extension of spatial modulation (SM) that conveys data information at multiple time instants. By encoding the permutation of activated antennas at several time instants, the SPM system gains benefits of transmit and time diversities enabling reliable mobile communications. This study proposed a low-complexity SPM detector, called multiple-candidate-selection matching maximal ratio combining detector (MCSMMRC), for the SPM system. The MCSMMRC detector has very low complexity, fixed throughput, and scalable computing structure, which makes MCSMMD suitable for hardware implementation. This study designed and implemented the proposed MCSMMD detector by using a Xilinx Virtex-7 FPGA chip. The FPGA implementation results showed that it achieved a maximum throughput of 538 Mbps and exhibited better normalized throughput than those of other SM-based detector chips in the literature.",
keywords = "Generalized spatial modulation (GSM), Multiple-input-multiple-output (MIMO), Spatial modulation (SM), Spatial permutation modulation (SPM)",
author = "Chi, {Jung Chun} and Yeh, {Yu Cheng} and Lai, {I. Wei} and Tsai, {Pei Yun} and Huang, {Yuan Hao}",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",
year = "2020",
language = "???core.languages.en_GB???",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",
}