A 5-11 GHz CMOS power amplifier using Guanella-type transmission line transformer and adaptive bias circuit

Hou An Lin; Yuan Chang Wang; Hwann Kaeo Chiou

doi:10.1002/mop.31510

A 5-11 GHz CMOS power amplifier using Guanella-type transmission line transformer and adaptive bias circuit

Hou An Lin, Yuan Chang Wang, Hwann Kaeo Chiou

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This paper presents a 5-11 GHz fully integrated power amplifier (PA) in tsmc 0.18 μm CMOS technology. The PA utilized broadband and low-loss Guanella differential transmission-line transformers (DTLTs) as the input- and output-matching networks to achieve broadband performance. The adaptive bias circuit was adopted to improve the linearity and power added efficiency (PAE) at power back-off region. The power gain and stability were enhanced by capacitive unilaterialized technique. The PA achieves an output 1-dB compression point (OP_1dB) of 21.75 dBm with 1-dB bandwidth from 5.5 to 10.5 GHz. The PAEs at peak and P_1dB are 21.3% and 23.9%, respectively. The chip dimensions, including all pads, are 1.79 × 1.04 mm².

Original language	English
Pages (from-to)	267-270
Number of pages	4
Journal	Microwave and Optical Technology Letters
Volume	61
Issue number	1
DOIs	https://doi.org/10.1002/mop.31510
State	Published - Jan 2019

Keywords

adaptive bias circuit
CMOS power amplifier
differential transmission-line transformer (DTLT)
neutralization

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10.1002/mop.31510

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title = "A 5-11 GHz CMOS power amplifier using Guanella-type transmission line transformer and adaptive bias circuit",

abstract = "This paper presents a 5-11 GHz fully integrated power amplifier (PA) in tsmc 0.18 μm CMOS technology. The PA utilized broadband and low-loss Guanella differential transmission-line transformers (DTLTs) as the input- and output-matching networks to achieve broadband performance. The adaptive bias circuit was adopted to improve the linearity and power added efficiency (PAE) at power back-off region. The power gain and stability were enhanced by capacitive unilaterialized technique. The PA achieves an output 1-dB compression point (OP1dB) of 21.75 dBm with 1-dB bandwidth from 5.5 to 10.5 GHz. The PAEs at peak and P1dB are 21.3% and 23.9%, respectively. The chip dimensions, including all pads, are 1.79 × 1.04 mm2.",

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AB - This paper presents a 5-11 GHz fully integrated power amplifier (PA) in tsmc 0.18 μm CMOS technology. The PA utilized broadband and low-loss Guanella differential transmission-line transformers (DTLTs) as the input- and output-matching networks to achieve broadband performance. The adaptive bias circuit was adopted to improve the linearity and power added efficiency (PAE) at power back-off region. The power gain and stability were enhanced by capacitive unilaterialized technique. The PA achieves an output 1-dB compression point (OP1dB) of 21.75 dBm with 1-dB bandwidth from 5.5 to 10.5 GHz. The PAEs at peak and P1dB are 21.3% and 23.9%, respectively. The chip dimensions, including all pads, are 1.79 × 1.04 mm2.

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KW - neutralization

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A 5-11 GHz CMOS power amplifier using Guanella-type transmission line transformer and adaptive bias circuit

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Keywords

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