A 4x4-block level pipeline and bandwidth optimized motion compensation hardware design for H.264/AVC DECODER

De Yuan Shen, Tsung Han Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A 4x4-block level pipeline motion compensation (MC) architecture for H.264/AVC decoder with high hardware utilization and low bandwidth requirement is presented in this paper. With the proposed Minimum Required Reference Data Loading (MRRD) and Data Reuse from Upper/Left block (DRUL) strategies, the memory bandwidth is reduced by 70% without violating the inherent double-z-scan order of H.264/AVC bitstream. The flexible FIR filters and row/column-based interpolation are adopted to enhance the hardware utilization. Besides, to improve the bus utilization and decoding time, an on-chip memory with transpose data access and memory preloaded techniques are used for reference data reuse. The proposed MC hardware can support 1920x1088 30fps 4x4-block level pipeline in H.264/AVC decoder with less than 60MB/s memory bandwidth and a 432-byte on-chip memory when operating at 100MHz.

Original languageEnglish
Title of host publicationProceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009
Pages1106-1109
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE International Conference on Multimedia and Expo, ICME 2009 - New York, NY, United States
Duration: 28 Jun 20093 Jul 2009

Publication series

NameProceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009

Conference

Conference2009 IEEE International Conference on Multimedia and Expo, ICME 2009
Country/TerritoryUnited States
CityNew York, NY
Period28/06/093/07/09

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