@inproceedings{9882dbe0915348609e20df8e5a098730,
title = "A 4x4-block level pipeline and bandwidth optimized motion compensation hardware design for H.264/AVC DECODER",
abstract = "A 4x4-block level pipeline motion compensation (MC) architecture for H.264/AVC decoder with high hardware utilization and low bandwidth requirement is presented in this paper. With the proposed Minimum Required Reference Data Loading (MRRD) and Data Reuse from Upper/Left block (DRUL) strategies, the memory bandwidth is reduced by 70% without violating the inherent double-z-scan order of H.264/AVC bitstream. The flexible FIR filters and row/column-based interpolation are adopted to enhance the hardware utilization. Besides, to improve the bus utilization and decoding time, an on-chip memory with transpose data access and memory preloaded techniques are used for reference data reuse. The proposed MC hardware can support 1920x1088 30fps 4x4-block level pipeline in H.264/AVC decoder with less than 60MB/s memory bandwidth and a 432-byte on-chip memory when operating at 100MHz.",
author = "Shen, {De Yuan} and Tsai, {Tsung Han}",
year = "2009",
doi = "10.1109/ICME.2009.5202692",
language = "???core.languages.en_GB???",
isbn = "9781424442911",
series = "Proceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009",
pages = "1106--1109",
booktitle = "Proceedings - 2009 IEEE International Conference on Multimedia and Expo, ICME 2009",
note = "2009 IEEE International Conference on Multimedia and Expo, ICME 2009 ; Conference date: 28-06-2009 Through 03-07-2009",
}