A 4x4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps

Pei Yun Tsai, Wei Tzuo Chen, Xing Cheng Lin, Meng Yuan Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

29 Scopus citations

Abstract

In this paper, a VLSI architecture of a reduced-complexity K-best sphere decoder is designed, which aims to solve the 4 x 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages3953-3956
Number of pages4
DOIs
StatePublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 30 May 20102 Jun 2010

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/TerritoryFrance
CityParis
Period30/05/102/06/10

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