A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Shyh Shyuan Sheu; Meng Fan Chang; Ku Feng Lin; Che Wei Wu; Yu Sheng Chen; Pi Feng Chiu; Chia Chen Kuo; Yih Shan Yang; Pei Chia Chiang; Wen Pin Lin; Che He Lin; Heng Yuan Lee; Pei Yi Gu; Sum Min Wang; Frederick T. Chen; Keng Li Su; Chen Hsin Lien; Kuo Hsing Cheng; Hsin Tun Wu; Tzu Kun Ku; Ming Jer Kao; Ming Jinn Tsai

doi:10.1109/ISSCC.2011.5746281

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Shyh Shyuan Sheu
, Meng Fan Chang
, Ku Feng Lin
, Che Wei Wu
, Yu Sheng Chen
, Pi Feng Chiu
, Chia Chen Kuo
, Yih Shan Yang
, Pei Chia Chiang
, Wen Pin Lin
, Che He Lin
, Heng Yuan Lee
, Pei Yi Gu
, Sum Min Wang
, Frederick T. Chen
, Keng Li Su
, Chen Hsin Lien
, Kuo Hsing Cheng
, Hsin Tun Wu
, Tzu Kun Ku

Ming Jer Kao, Ming Jinn Tsai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

244 Scopus citations

Abstract

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (V_BL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

Original language	English
Title of host publication	2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	200-202
Number of pages	3
ISBN (Print)	9781612843001
DOIs	https://doi.org/10.1109/ISSCC.2011.5746281
State	Published - 2011
Event	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States Duration: 20 Feb 2011 → 24 Feb 2011

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Country/Territory	United States
City	San Francisco
Period	20/02/11 → 24/02/11

Access to Document

10.1109/ISSCC.2011.5746281

Cite this

Sheu, S. S., Chang, M. F., Lin, K. F., Wu, C. W., Chen, Y. S., Chiu, P. F., Kuo, C. C., Yang, Y. S., Chiang, P. C., Lin, W. P., Lin, C. H., Lee, H. Y., Gu, P. Y., Wang, S. M., Chen, F. T., Su, K. L., Lien, C. H., Cheng, K. H., Wu, H. T., ... Tsai, M. J. (2011). A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 200-202). Article 5746281 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2011.5746281

Sheu, Shyh Shyuan ; Chang, Meng Fan ; Lin, Ku Feng et al. / A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. pp. 200-202 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{5c5aacc8375e495a96c00eb8a771427e,

title = "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability",

abstract = "Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.",

author = "Sheu, \{Shyh Shyuan\} and Chang, \{Meng Fan\} and Lin, \{Ku Feng\} and Wu, \{Che Wei\} and Chen, \{Yu Sheng\} and Chiu, \{Pi Feng\} and Kuo, \{Chia Chen\} and Yang, \{Yih Shan\} and Chiang, \{Pei Chia\} and Lin, \{Wen Pin\} and Lin, \{Che He\} and Lee, \{Heng Yuan\} and Gu, \{Pei Yi\} and Wang, \{Sum Min\} and Chen, \{Frederick T.\} and Su, \{Keng Li\} and Lien, \{Chen Hsin\} and Cheng, \{Kuo Hsing\} and Wu, \{Hsin Tun\} and Ku, \{Tzu Kun\} and Kao, \{Ming Jer\} and Tsai, \{Ming Jinn\}",

year = "2011",

doi = "10.1109/ISSCC.2011.5746281",

language = "???core.languages.en\_GB???",

isbn = "9781612843001",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "200--202",

booktitle = "2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011",

note = "2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 ; Conference date: 20-02-2011 Through 24-02-2011",

}

Sheu, SS, Chang, MF, Lin, KF, Wu, CW, Chen, YS, Chiu, PF, Kuo, CC, Yang, YS, Chiang, PC, Lin, WP, Lin, CH, Lee, HY, Gu, PY, Wang, SM, Chen, FT, Su, KL, Lien, CH, Cheng, KH, Wu, HT, Ku, TK, Kao, MJ & Tsai, MJ 2011, A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. in 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011., 5746281, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 200-202, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, United States, 20/02/11. https://doi.org/10.1109/ISSCC.2011.5746281

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. / Sheu, Shyh Shyuan; Chang, Meng Fan; Lin, Ku Feng et al.
2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 200-202 5746281 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

AU - Sheu, Shyh Shyuan

AU - Chang, Meng Fan

AU - Lin, Ku Feng

AU - Wu, Che Wei

AU - Chen, Yu Sheng

AU - Chiu, Pi Feng

AU - Kuo, Chia Chen

AU - Yang, Yih Shan

AU - Chiang, Pei Chia

AU - Lin, Wen Pin

AU - Lin, Che He

AU - Lee, Heng Yuan

AU - Gu, Pei Yi

AU - Wang, Sum Min

AU - Chen, Frederick T.

AU - Su, Keng Li

AU - Lien, Chen Hsin

AU - Cheng, Kuo Hsing

AU - Wu, Hsin Tun

AU - Ku, Tzu Kun

AU - Kao, Ming Jer

AU - Tsai, Ming Jinn

PY - 2011

Y1 - 2011

N2 - Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

AB - Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

UR - https://www.scopus.com/pages/publications/79955726402

U2 - 10.1109/ISSCC.2011.5746281

DO - 10.1109/ISSCC.2011.5746281

M3 - 會議論文篇章

AN - SCOPUS:79955726402

SN - 9781612843001

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 200

EP - 202

BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011

Y2 - 20 February 2011 through 24 February 2011

ER -

Sheu SS, Chang MF, Lin KF, Wu CW, Chen YS, Chiu PF et al. A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. Institute of Electrical and Electronics Engineers Inc. 2011. p. 200-202. 5746281. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2011.5746281

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this