A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Shyh Shyuan Sheu, Meng Fan Chang, Ku Feng Lin, Che Wei Wu, Yu Sheng Chen, Pi Feng Chiu, Chia Chen Kuo, Yih Shan Yang, Pei Chia Chiang, Wen Pin Lin, Che He Lin, Heng Yuan Lee, Pei Yi Gu, Sum Min Wang, Frederick T. Chen, Keng Li Su, Chen Hsin Lien, Kuo Hsing Cheng, Hsin Tun Wu, Tzu Kun KuMing Jer Kao, Ming Jinn Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

233 Scopus citations

Abstract

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1-3], MRAM [4-5], and resistive RAM (RRAM) [6-8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

Original languageEnglish
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages200-202
Number of pages3
ISBN (Print)9781612843001
DOIs
StatePublished - 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States
Duration: 20 Feb 201124 Feb 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Country/TerritoryUnited States
CitySan Francisco
Period20/02/1124/02/11

Fingerprint

Dive into the research topics of 'A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability'. Together they form a unique fingerprint.

Cite this