@inproceedings{6e700ed07baa4e6cae71785a1ad7d79c,
title = "A 3.5-GHz 6-Bit CMOS Vector-Summing Phase Shifter with Low Phase and Amplitude Errors Using Area-Resizing Technique",
abstract = "For a vector-summing phase shifter (VSPS), if the gain of its variable gain amplifiers (VGAs) can be adjusted with fine resolution, low phase and amplitude errors can both be achieved. By adopting area-resizing technique for the design of the VGAs, a 6-bit VSPS is realized using a 0.18-µm CMOS process. Measurement results of the phase shifter show that the RMS phase error is less than 3° and the RMS amplitude error is less than 0.4 dB for more than 2:1 bandwidth.",
keywords = "area resizing, phase shifter, vector summing",
author = "Hsu, {Chia Wei} and Fu, {Jia Shiang}",
note = "Publisher Copyright: {\textcopyright} 2022 The Institute of Electronics Information and Communication Engineers (IEICE) of Japan.; 2022 Asia-Pacific Microwave Conference, APMC 2022 ; Conference date: 29-11-2022 Through 02-12-2022",
year = "2022",
language = "???core.languages.en_GB???",
series = "Asia-Pacific Microwave Conference Proceedings, APMC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "701--703",
booktitle = "2022 Asia-Pacific Microwave Conference, APMC 2022 - Proceedings",
}