A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery

Kuo Hsing Cheng; Chao An Chen; Wei Bin Yang; Feng Hsin Cho

doi:10.1109/VDAT.2007.373236

A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery

Kuo Hsing Cheng, Chao An Chen, Wei Bin Yang, Feng Hsin Cho

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p.8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.

Original language	English
Title of host publication	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VDAT.2007.373236
State	Published - 2007
Event	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan Duration: 25 Apr 2007 → 27 Apr 2007

Publication series

Name	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference	2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/07 → 27/04/07

Access to Document

10.1109/VDAT.2007.373236

Cite this

Cheng, K. H., Chen, C. A., Yang, W. B., & Cho, F. H. (2007). A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers Article 4239428 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373236

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title = "A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery",

abstract = "In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p.8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.",

author = "Cheng, {Kuo Hsing} and Chen, {Chao An} and Yang, {Wei Bin} and Cho, {Feng Hsin}",

year = "2007",

doi = "10.1109/VDAT.2007.373236",

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isbn = "1424405831",

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booktitle = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers",

note = "2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 ; Conference date: 25-04-2007 Through 27-04-2007",

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Cheng, KH, Chen, CA, Yang, WB & Cho, FH 2007, A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery. in 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers., 4239428, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, Hsinchu, Taiwan, 25/04/07. https://doi.org/10.1109/VDAT.2007.373236

A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery. / Cheng, Kuo Hsing; Chen, Chao An; Yang, Wei Bin et al.
2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239428 (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p.8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.

AB - In this paper, we present architecture of phase-locked loop (PLL) for clock and data recovery (CDR) for high-speed serial links. The conventional over-sampling architecture uses two timing modules. One is used to track reference clock, the other is to generate multiphase to sample high speed serial-in data. The architecture improves drawback of the conventional CDR by using Blender unit to make high resolution delay phase and PLL will track this phase. Additionally, this work achieves to save power and chip area and the stability of system can be improved, because of combining the two timing modules to one. This work is fabricated by TSMC 0.13um 1p.8m 1.2v process. The PLL is operates at 500MHz and CDR circuit can recovery 5Gb/s serial-in data.

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Cheng KH, Chen CA, Yang WB, Cho FH. A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 2007. 4239428. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2007.373236

A 30PHASE 500MHZ PLL for 3X over-sampling clock data recovery

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