A 3 GHz DLL-based clock generator with stuck locking protection

Yo Hao Tu, Hsiang Hao Chang, Cheng Liang Hung, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This study presents a 3-GHz DLL-based clock generator with stuck locking protection. In this paper, a proposed duty cycle corrector solves the problem of the sensitivity to half transparent (HT) architecture and the stuck locking error in the DLL simultaneously. Based on the frequency-multiplied technique, the multiphase DLL architecture synthesizes a 3-GHz output clock. The post-layout simulation results are based on TSMC 0.18 μm 1P6M CMOS process. The proposed architecture locks into the input frequency of 250 MHz. Operating at the 3-GHz frequency multiplier output, the simulated peak-to-peak jitter is 2.94 ps and 31.17 ps for the 250-MHz locked frequency and 3-GHz synthesized frequency, respectively. The chip area is less than 0.745 × 0.745 mm 2 and the power consumption is 20.9 m W at a supply of 1.8 V.

Original languageEnglish
Title of host publication2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings
Pages106-109
Number of pages4
DOIs
StatePublished - 2010
Event2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Athens, Greece
Duration: 12 Dec 201015 Dec 2010

Publication series

Name2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings

Conference

Conference2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010
Country/TerritoryGreece
CityAthens
Period12/12/1015/12/10

Keywords

  • Delay-locked loop (DLL)
  • Duty cycle corrector (DCC)
  • Frequency multiplier (FM)
  • Half transparent (HT)
  • Stuck locking

Fingerprint

Dive into the research topics of 'A 3 GHz DLL-based clock generator with stuck locking protection'. Together they form a unique fingerprint.

Cite this