A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Ting Chen Wei; Wei Chang Liu; Chi Yao Tseng; Syu Siang Long; Shyh Jye Jou; Muh Tian Shiue

doi:10.1109/CICC.2008.4672094

A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Ting Chen Wei, Wei Chang Liu, Chi Yao Tseng, Syu Siang Long, Shyh Jye Jou, Muh Tian Shiue

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.

Original language	English
Article number	4672094
Pages (from-to)	351-354
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672094
State	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: 21 Sep 2008 → 24 Sep 2008

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title = "A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization",

abstract = "An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.",

author = "Wei, {Ting Chen} and Liu, {Wei Chang} and Tseng, {Chi Yao} and Long, {Syu Siang} and Jou, {Shyh Jye} and Shiue, {Muh Tian}",

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T1 - A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

AU - Wei, Ting Chen

AU - Liu, Wei Chang

AU - Tseng, Chi Yao

AU - Long, Syu Siang

AU - Jou, Shyh Jye

AU - Shiue, Muh Tian

PY - 2008

Y1 - 2008

N2 - An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.

AB - An OFDM baseband receiver chip for DVB-T/H application is proposed In this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and ± 50 subcarrier spacing carrier frequency offset (CFO) In multipath environment. The total memory requirement of this chip is 102.8KB and the total equivalent gate count (Including memory) is about 806,800 gates. By using 0.18μm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600μm × 3600μm.

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M3 - 會議論文

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SN - 0886-5930

SP - 351

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JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

M1 - 4672094

T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008

Y2 - 21 September 2008 through 24 September 2008

ER -

A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

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