A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN

Fang Li Yuan; Yi Hsien Lin; Chih Feng Wu; Muh Tian Shiue; Chorng Kuang Wang

doi:10.1109/ASSCC.2008.4708789

A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN

Fang Li Yuan, Yi Hsien Lin, Chih Feng Wu, Muh Tian Shiue, Chorng Kuang Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

In this paper, an efficient solution of MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. The proposed FFT/IFFT processor has been emulated on the FPGA board. The signalto-quantization noise ratio (SQNR) is over 44 dB for QPSK and 16/64-QAM signals. Furthermore, a test chip has been designed using standard 0.18-μm CMOS technology with a core area of 887×842 μm². According to the post-layout simulation results, the design consumes 46 mW at 64 MHz operating frequency, which meets the maximum throughput requirements of IEEE 802.16 WMAN.

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	309-312
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708789
State	Published - 2008
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 3 Nov 2008 → 5 Nov 2008

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Conference

Conference	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	3/11/08 → 5/11/08

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10.1109/ASSCC.2008.4708789

Cite this

Yuan, F. L., Lin, Y. H., Wu, C. F., Shiue, M. T., & Wang, C. K. (2008). A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 309-312). Article 4708789 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708789

@inproceedings{a39e02349a264cc89bb904c08dd6b543,

title = "A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN",

abstract = "In this paper, an efficient solution of MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. The proposed FFT/IFFT processor has been emulated on the FPGA board. The signalto-quantization noise ratio (SQNR) is over 44 dB for QPSK and 16/64-QAM signals. Furthermore, a test chip has been designed using standard 0.18-μm CMOS technology with a core area of 887×842 μm2. According to the post-layout simulation results, the design consumes 46 mW at 64 MHz operating frequency, which meets the maximum throughput requirements of IEEE 802.16 WMAN.",

author = "Yuan, {Fang Li} and Lin, {Yi Hsien} and Wu, {Chih Feng} and Shiue, {Muh Tian} and Wang, {Chorng Kuang}",

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isbn = "9781424426058",

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pages = "309--312",

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note = "2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 ; Conference date: 03-11-2008 Through 05-11-2008",

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Yuan, FL, Lin, YH, Wu, CF, Shiue, MT & Wang, CK 2008, A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708789, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 309-312, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 3/11/08. https://doi.org/10.1109/ASSCC.2008.4708789

A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN. / Yuan, Fang Li; Lin, Yi Hsien; Wu, Chih Feng et al.
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 309-312 4708789 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN

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