A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop using 65 nm CMOS process

Keyphrases

• CMOS Process 100%
• Self-aligned 100%
• 65nm CMOS 100%
• Injection-locked Phase-locked Loop 100%
• Frequency Variation 50%
• Delay-locked Loop 50%
• Low Jitter 50%
• Phase Noise 50%
• Phase Difference 50%
• Temperature Variation 50%
• Low Phase Noise 50%
• Voltage-controlled Oscillator 50%
• Phase-locked Loop 50%
• Injection Signal 50%
• Injection Locking 50%
• Quality Robustness 50%
• RMS Jitter 50%

Engineering

• Phase Locked Loop 100%
• Phase Noise 66%
• Locked Loop 33%
• Phase Difference 33%
• Voltage-Controlled Oscillator 33%
• Measured Phase 33%
• Rms Jitter 33%