@inproceedings{8d558c6435f04dcaa0bfbbe8f9b11fdd,
title = "A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop using 65 nm CMOS process",
abstract = "A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the measured phase noises at 1 kHz, 10 kHz, 100 kHz, and 1 MHz offset are better than-110,-112,-122 and-128.4 dBc/Hz, respectively, with an rms jitter of 228 fs. This work demonstrates low phase noise, low jitter, and good robustness over frequency and temperature variations.",
keywords = "CMOS, DLL, PLL, VCO, low jitter, low phase noise",
author = "Yeh, {Yen Liang} and Lu, {Cheng Han} and Li, {Meng Han} and Chang, {Hong Yeh} and Kevin Chen",
note = "Publisher Copyright: {\textcopyright} 2014 European Microwave Association-EUMA.; 9th European Microwave Integrated Circuits Conference, EuMIC 2014 - Held as Part of the 17th European Microwave Week, EuMW 2014 ; Conference date: 06-10-2014 Through 07-10-2014",
year = "2014",
month = dec,
day = "23",
doi = "10.1109/EuMIC.2014.6997844",
language = "???core.languages.en_GB???",
series = "European Microwave Week 2014: {"}Connecting the Future{"}, EuMW 2014 - Conference Proceedings; EuMIC 2014: 9th European Microwave Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "269--272",
booktitle = "European Microwave Week 2014",
}