A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop using 65 nm CMOS process

Yen Liang Yeh, Cheng Han Lu, Meng Han Li, Hong Yeh Chang, Kevin Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the measured phase noises at 1 kHz, 10 kHz, 100 kHz, and 1 MHz offset are better than-110,-112,-122 and-128.4 dBc/Hz, respectively, with an rms jitter of 228 fs. This work demonstrates low phase noise, low jitter, and good robustness over frequency and temperature variations.

Original languageEnglish
Title of host publicationEuropean Microwave Week 2014
Subtitle of host publication"Connecting the Future", EuMW 2014 - Conference Proceedings; EuMIC 2014: 9th European Microwave Integrated Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages269-272
Number of pages4
ISBN (Electronic)9782874870361
DOIs
StatePublished - 23 Dec 2014
Event9th European Microwave Integrated Circuits Conference, EuMIC 2014 - Held as Part of the 17th European Microwave Week, EuMW 2014 - Rome, Italy
Duration: 6 Oct 20147 Oct 2014

Publication series

NameEuropean Microwave Week 2014: "Connecting the Future", EuMW 2014 - Conference Proceedings; EuMIC 2014: 9th European Microwave Integrated Circuits Conference

Conference

Conference9th European Microwave Integrated Circuits Conference, EuMIC 2014 - Held as Part of the 17th European Microwave Week, EuMW 2014
Country/TerritoryItaly
CityRome
Period6/10/147/10/14

Keywords

  • CMOS
  • DLL
  • low jitter
  • low phase noise
  • PLL
  • VCO

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