A 20-to-60 GHz CMOS frequency tripler based on a BPSK modulator

Fan Hsiu Huang, Chin Cheng Chen, Hong Yeh Chang, Yue Ming Hsin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A frequency tripler designed for V-band signal generation has been implemented by using CMOS 0.18 μ m process. Based on the circuit topology of differential binary phase shift keying (BPSK) modulator, a function of frequency triplication can be performed under the operation modes of class-AB and class-C when choosing the proper biases on the NMOS devices. For achieving a large 60 GHz output signal, the compact impedance matching network based on the imbalanced transmission-line is also used to the output port. The tripler exhibits a measured conversion loss about 9.4 dB under a 2 dBm injected power with a dc power consumption of 16 mW from a 2 V dc supply. The output 3-dB bandwidth is around 7 GHz ranging from 56 to 63 GHz, and the maximum output power can be operated up to -7 dBm. The suppression ratios for fundamental and second harmonics are exhibited up to 17 dBc and 25 dBc, respectively. The BPSK digital modulation at 60 GHz is also demonstrated with a data rate of 1 Gbps.

Original languageEnglish
Title of host publicationAPMC 2009 - Asia Pacific Microwave Conference 2009
Pages2264-2267
Number of pages4
DOIs
StatePublished - 2009
EventAsia Pacific Microwave Conference 2009, APMC 2009 - Singapore, Singapore
Duration: 7 Dec 200910 Dec 2009

Publication series

NameAPMC 2009 - Asia Pacific Microwave Conference 2009

Conference

ConferenceAsia Pacific Microwave Conference 2009, APMC 2009
Country/TerritorySingapore
CitySingapore
Period7/12/0910/12/09

Keywords

  • CMOS
  • Frequency conversion
  • Millimeter-wave signal generation

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