A frequency tripler designed for V-band signal generation has been implemented by using CMOS 0.18 μ m process. Based on the circuit topology of differential binary phase shift keying (BPSK) modulator, a function of frequency triplication can be performed under the operation modes of class-AB and class-C when choosing the proper biases on the NMOS devices. For achieving a large 60 GHz output signal, the compact impedance matching network based on the imbalanced transmission-line is also used to the output port. The tripler exhibits a measured conversion loss about 9.4 dB under a 2 dBm injected power with a dc power consumption of 16 mW from a 2 V dc supply. The output 3-dB bandwidth is around 7 GHz ranging from 56 to 63 GHz, and the maximum output power can be operated up to -7 dBm. The suppression ratios for fundamental and second harmonics are exhibited up to 17 dBc and 25 dBc, respectively. The BPSK digital modulation at 60 GHz is also demonstrated with a data rate of 1 Gbps.