A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique

Jia Ching Wang, Tsung Chih Hung, Tai Haur Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a 15-bit pipelined ADC using the averaging correlated level shifting (Averaging-CLS) technique for reducing finite opamp gain error and opamp thermal noise. Adopting the Averaging-CLS technique enables an ADC to use a medium-accuracy amplifier structure in a high-resolution ADC. Furthermore, the front-end sample-and-hold amplifier (SHA) is removed to reduce power consumption and cost. The 15-bit pipelined ADC was fabricated by 90 nm CMOS. The measured peak SNDR achieves 73.7 dB at a 20 MS/s sampling rate and the ADC consumes 4.7 mW, leading to the Walden and Schreier Figure-of-Merits of 59.4 fJ/conv.-step and 167 dB, respectively.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
StatePublished - Apr 2019
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 22 Apr 201925 Apr 2019

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/TerritoryTaiwan
CityHsinchu
Period22/04/1925/04/19

Keywords

  • Analog-to-digital converter (ADC)
  • Averaging correlated level shifting (Averaging-CLS)
  • Correlated level shifting (CLS)
  • Pipelined ADC
  • Ring amplifier

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