A 100 MHz-1 GHz adaptive bandwidth PLL using TDC technique

Kuo Hsing Cheng, Yu Lung Lo, Ching Wen Lai, Wei Bin Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In phase-locked loop (PLL), the loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this paper employs formula derives to find the relationship between the loop parameters. Therefore, the PLL uses time-to-digital converter (TDC) and programmable current mirror (PCM) to adjust loop parameters that can apply to provide the wide operating frequency range and low-jitter performance. The chip is fabricated in a 0.18-μm standard CMOS process with a 1.8 V power supply voltage and consumes 8 mW at 400 MHz operation frequency. The measured output operating frequency range is 100 MHz-1 GHz, the input reference frequency range is 5 MHz-100 MHz, and the jitter is less than 3.3% of the output period.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages1163-1166
Number of pages4
DOIs
StatePublished - 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/TerritoryMorocco
CityMarrakech
Period11/12/0714/12/07

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