A 1-V 5-GHz self-bias folded-switch mixer in 90-nm CMOS for WLAN receiver

Hwann Kaeo Chiou, Kuei Cheng Lin, Wei Hsien Chen, Ying Zong Juang

Research output: Contribution to journalArticlepeer-review

30 Scopus citations

Abstract

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP2) and IIP3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively.

Original languageEnglish
Article number6104398
Pages (from-to)1215-1227
Number of pages13
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number6
DOIs
StatePublished - 2012

Keywords

  • AC coupling
  • CMOS
  • current reuse
  • direct-conversion receiver
  • double balanced mixer
  • folded-switch mixer
  • low voltage

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