A 0.6-V 800-MHz all-digital phase-locked loop with a digital supply regulator

Kuo Hsing Cheng, Jen Chieh Liu, Hong Yi Huang

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

This paper proposes an ultra-low-voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator (DSR). The DSR maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution. The proposed digital loop filter can reduce the area cost and critical path using the double-edge trigger technique. For a low supply voltage, the DCO and the time-to-digital converter use bulk-controlled techniques to increase the highest operating frequency and timing resolution, respectively. When the ADPLL output is 800 MHz at 0.6 V, the power consumption and core area are 656 μW and 0.02 mm2, respectively, in a 90-nm CMOS process.

Original languageEnglish
Article number6407963
Pages (from-to)888-892
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume59
Issue number12
DOIs
StatePublished - 2012

Keywords

  • All-digital PLL (ADPLL)
  • digital controlled varactor (DCV)
  • digital loop filter (DLF)
  • digital supply regulator (DSR)

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