A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

Yo Hao Tu, Jen Chieh Liu, Kuo Hsing Cheng, Hong Yi Huang, Chang Chien Hu

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.

Original languageEnglish
Article number20150950
JournalIEICE Electronics Express
Issue number2
StatePublished - 22 Dec 2015


  • All-digital phase-locked loop (ADPLL)
  • Digital controlled oscillator (DCO)
  • Low supply voltage
  • Multi-phase outputs
  • Time amplifier (TA)
  • Time-to-digital converter (TDC)


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