A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

Yo Hao Tu, Jen Chieh Liu, Kuo Hsing Cheng, Chih Hsun Hsu

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.

Original languageEnglish
Pages (from-to)157-167
Number of pages11
JournalAnalog Integrated Circuits and Signal Processing
Volume93
Issue number1
DOIs
StatePublished - 1 Oct 2017

Keywords

  • I/Q clock signals
  • Low supply voltage
  • Quadrature phase output
  • Synchronous circuit

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