A 0.3-V all digital crystal-less clock generator for energy harvester applications

Jen Chieh Liu, Wei Chun Lee, Hong Yi Huang, Kuo Hsing Cheng, Chao Jen Huang, Yu Wei Liang, Jia Hung Peng, Yuan Hua Chu

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations

Abstract

A 0.3 V all digital crystal-less clock generator (CLCG) is presented for a hearing aid application. The all digital CLCG uses frequency difference between the ring oscillator and the digital controlled oscillator (DCO) to create a mapping table under process and temperature variations. The digital loop filter (DLF) adopts a successive-approximation register (SAR) algorithm for fast locking time. Thus, the worse case of locking time is 73 output cycles. For a hearing aid application, the core area of CLCG and hearing aid system are 62 × 78 μm2 and 1900 × 1920 μm2, respectively, in 65 nm CMOS process. The frequency accuracy is 12 MHz ±3.5% in four test chips. The power consumption is 5 μW. In the period jitter, the RMS and peak-to-peak jitters are 326.4 ps and 2.05 ns, respectively. The frequency drift is smaller than ±4.3% from 0 to 100°C. Thus, this work is also used for energy harvester applications.

Original languageEnglish
Pages117-120
Number of pages4
DOIs
StatePublished - 2012
Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
Duration: 12 Nov 201214 Nov 2012

Conference

Conference2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
Country/TerritoryJapan
CityKobe
Period12/11/1214/11/12

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