A 0.3 V all digital crystal-less clock generator (CLCG) is presented for a hearing aid application. The all digital CLCG uses frequency difference between the ring oscillator and the digital controlled oscillator (DCO) to create a mapping table under process and temperature variations. The digital loop filter (DLF) adopts a successive-approximation register (SAR) algorithm for fast locking time. Thus, the worse case of locking time is 73 output cycles. For a hearing aid application, the core area of CLCG and hearing aid system are 62 × 78 μm2 and 1900 × 1920 μm2, respectively, in 65 nm CMOS process. The frequency accuracy is 12 MHz ±3.5% in four test chips. The power consumption is 5 μW. In the period jitter, the RMS and peak-to-peak jitters are 326.4 ps and 2.05 ns, respectively. The frequency drift is smaller than ±4.3% from 0 to 100°C. Thus, this work is also used for energy harvester applications.
|Number of pages||4|
|State||Published - 2012|
|Event||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan|
Duration: 12 Nov 2012 → 14 Nov 2012
|Conference||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012|
|Period||12/11/12 → 14/11/12|