A 0.18-μm dual-gate CMOS device modeling and applications for RF cascode circuits

Hong Yeh Chang, Kung Hao Liang

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the distributed resistances, and the inductances, are extracted from the measured S-parameters. In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is also evaluated with power sweep and loadpull measurements. In addition, a doubly balanced dual-gate mixer is successfully demonstrated using the proposed model. The measured results agree with the simulated results using the proposed device model for both linear and nonlinear applications. The advanced large-signal dual-gate CMOS model can be further used as an RF sub-circuit cell for simplifying the design procedure.

Original languageEnglish
Article number5654608
Pages (from-to)116-124
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Issue number1
StatePublished - Jan 2011


  • BSIM
  • CMOS
  • dual gate
  • low-noise amplifier (LNA)
  • mixer
  • modeling


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