64-Bit hybrid dual-threshold voltage power-aware conditional carry adder design

Kuo Hsing Cheng, Shun Wen Cheng, Chan Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A 64-bit hybrid dual-threshold conditional-carry adder for power-aware applications was presented. Components on critical paths use a low threshold voltage to accelerate the speed of operation. Other components use the normal threshold voltage to save power. This is attractive in implementing power-aware arithmetic systems. The proposed circuit has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
EditorsW. Badawy, Y. Ismail
Pages65-68
Number of pages4
StatePublished - 2004
EventProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 - Banff, Alta, Canada
Duration: 19 Jul 200421 Jul 2004

Publication series

NameProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

Conference

ConferenceProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
Country/TerritoryCanada
CityBanff, Alta
Period19/07/0421/07/04

Keywords

  • Adder
  • CMOS
  • Conditional carry
  • Hybrid dual-threshold voltage
  • VLSI design

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