@inproceedings{f2adaf531d9a4584936ba5161fc53c6a,
title = "64-Bit hybrid dual-threshold voltage power-aware conditional carry adder design",
abstract = "A 64-bit hybrid dual-threshold conditional-carry adder for power-aware applications was presented. Components on critical paths use a low threshold voltage to accelerate the speed of operation. Other components use the normal threshold voltage to save power. This is attractive in implementing power-aware arithmetic systems. The proposed circuit has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.",
keywords = "Adder, CMOS, Conditional carry, Hybrid dual-threshold voltage, VLSI design",
author = "Cheng, {Kuo Hsing} and Cheng, {Shun Wen} and Huang, {Chan Wei}",
year = "2004",
language = "???core.languages.en_GB???",
isbn = "0769521827",
series = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004",
pages = "65--68",
editor = "W. Badawy and Y. Ismail",
booktitle = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004",
note = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 ; Conference date: 19-07-2004 Through 21-07-2004",
}