64-bit high-performance power-aware conditional carry adder design

Kuo Hsing Cheng, Shun Wen Cheng

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The conditional sum adder (CSA) has been shown to outperform other adders applied in high-speed applications. This investigation proposes a modified CSA called the conditional carry adder (CCA). Based on the proposed adder architecture, six 64-bit hybrid dual-threshold CCAs for power-aware applications were discussed. Architectural modification of the CCA raises the operation speed, decreases the power dissipation, and lowers the hardware overhead. The proposed 64-bit CCA can decrease the number of multiplexers and internal nodes in the adder design by around 27% compared to the 64-bit CSA. Furthermore, components on critical paths use a low threshold voltage to accelerate the speed of operation, and other components use the normal threshold voltage to save power. This feature is very useful in implementing power-aware arithmetic systems. One of the proposed circuits has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.

Original languageEnglish
Pages (from-to)1322-1331
Number of pages10
JournalIEICE Transactions on Electronics
VolumeE88-C
Issue number6
DOIs
StatePublished - Jun 2005

Keywords

  • CMOS design
  • Conditional carry adder
  • Conditional sum adder
  • Hybrid dual-threshold voltage
  • Power-aware

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