3-D content addressable memory architectures

Yong Jyun Hu, Jin Fu Li, Yu Jen Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Three-dimensional (3-D) integration is an emerging integrated circuit technology. Semiconductor memory is very suitable to be realized using 3-D technology due to its regularity. Different from random access memories (RAMs), a content addressable memory (CAM) has a priority address encoder (PAE) for evaluating the comparison result. The existing of PAE causes that the design of 3-D architectures for CAMs is more difficult than that for RAMs. This paper proposes a matchline-partitioned 3-D architecture and a searchline-partitioned 3-D architectures for CAMs. An inter-layer interleaving scheme is proposed to distribute PAE logic circuits evenly in two layers such that the footprint of a 3-D CAM is minimized. Experimental results show that the proposed 3-D CAM have better search performance for most of CAMs used in the industry.

Original languageEnglish
Title of host publicationProceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Pages59-64
Number of pages6
DOIs
StatePublished - 2009
Event2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan
Duration: 31 Aug 20092 Sep 2009

Publication series

NameProceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Conference

Conference2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Country/TerritoryTaiwan
CityHsinchu
Period31/08/092/09/09

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