@inproceedings{2d301532254d480a83b36dc4532c7036,
title = "3-D content addressable memory architectures",
abstract = "Three-dimensional (3-D) integration is an emerging integrated circuit technology. Semiconductor memory is very suitable to be realized using 3-D technology due to its regularity. Different from random access memories (RAMs), a content addressable memory (CAM) has a priority address encoder (PAE) for evaluating the comparison result. The existing of PAE causes that the design of 3-D architectures for CAMs is more difficult than that for RAMs. This paper proposes a matchline-partitioned 3-D architecture and a searchline-partitioned 3-D architectures for CAMs. An inter-layer interleaving scheme is proposed to distribute PAE logic circuits evenly in two layers such that the footprint of a 3-D CAM is minimized. Experimental results show that the proposed 3-D CAM have better search performance for most of CAMs used in the industry.",
author = "Hu, {Yong Jyun} and Li, {Jin Fu} and Huang, {Yu Jen}",
year = "2009",
doi = "10.1109/MTDT.2009.20",
language = "???core.languages.en_GB???",
isbn = "9780769537979",
series = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",
pages = "59--64",
booktitle = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",
note = "2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 ; Conference date: 31-08-2009 Through 02-09-2009",
}