0.5V 160-MHz 260uW all digital phase-locked loop

Jen Chieh Liu, Hong Yi Huang, Wei Bin Yang, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

Original languageEnglish
Title of host publicationProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
Pages186-189
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 - Liberec, Czech Republic
Duration: 15 Apr 200917 Apr 2009

Publication series

NameProceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009

Conference

Conference2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
Country/TerritoryCzech Republic
CityLiberec
Period15/04/0917/04/09

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