@inproceedings{863fd1dde14e4889abfd88509cf1f95d,
title = "0.5V 160-MHz 260uW all digital phase-locked loop",
abstract = "A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.",
author = "Liu, {Jen Chieh} and Huang, {Hong Yi} and Yang, {Wei Bin} and Cheng, {Kuo Hsing}",
year = "2009",
doi = "10.1109/DDECS.2009.5012125",
language = "???core.languages.en_GB???",
isbn = "9781424433391",
series = "Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009",
pages = "186--189",
booktitle = "Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009",
note = "2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 ; Conference date: 15-04-2009 Through 17-04-2009",
}