In the IC design process, the test process is a step that does not contain high technology but is unavoidable. The test process is depended on the customer who need to analyze the testing data to determine the situation of process, which will consume additional time cost and human resources. Therefore, the goal of the first half of the year of this plan is to develop a strengthen data analysis and wafer map defact classification base on deep learning neural network. Through the dataset is construct by collecting IC electrical parameters, wafer maps and the reason caused the error to build the neural network model. Finally, the IC electrical parameters and wafer maps are from dataset will be the input of our model. We expect to get the correct classification. This result will help us to speculate the reason that caused error to optimize the test process.The goal the second half of the year of the plan is to improve the performance of our model, and design a system that can integrate the label of dataset, data visualization and the test equipment, then we will combine with our model and this system. When the model detects the error, the system can give instructions to the relevant test equipment on time to reduce the cost of test process. The system can also provide the function of retrain model to handle with new defects in the future, that make model can be updated at any time.
|Effective start/end date
|1/06/20 → 31/05/21
- strengthen data analysis
- wafer map defact classification
- neural network
- Integrated test system
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