Van Der Waals Epitaxy of Gan for Electronic Device Applications(1/3)

With the advancements and growth of 5G mobile communications, renewable energy, cloud computing, electric/autonomous vehicles, artificial intelligence, robots, internet of things, a rapid growth of GaN-based power electronics and RF devices in the next few years is foreseen. However, current GaN RF devices are mainly developed on SiC substrate, which is insulating but limited by size and cost. As to the power electronics sector, GaN-on-Si is considered a competitive platform, on which lateral devices are developed and have been deployed. Due to the mismatch in thermal expansion coefficient between GaN and Si, the thickness of GaN is limited, therefore lateral devices are limited to applications below 900 V. For higher power applications, vertical devices on GaN substrate are under extensive development. However, the cost and size of GaN substrates available currently make these devices even more expensive than their SiC counterpart. This project aims at a new approach to resolve the aforementioned issues caused by the substrates. We plan to grow GaN films on poly-AlN substrates and (111)/(100) Si substrates, which are covered by graphene and/or h-BN 2D materials, using metal-organic vapor deposition. This is a van der Waals epitaxy process, a very challenging task while giving us an opportunity create a disruptive technology in the GaN device field. The poly-AlN substrate has not only high resistivity, high thermal conductivity, large wafer size up to 200 mm produced in a mass production scale by a local vendor, but also low thermal expansion coefficient mismatch with GaN, which allows a the growth of GaN up to several tens of um as required for high blocking voltage devices. Millimeter wave transistors are expected to perform better when this substrate is used. Growth parameters for GaN grown on both (111) and (100) Si substrates will also be explored in this work. The adoption of mainstream (100) Si substrates used current CMOS fab is expected to lower the cost as well as pave a way for heterogeneous integration with logic and mixed signal microchips.