Low power consumption is one key requirement for the Internet of Thing (IoT) applications. Insystem-on-chips (SoCs), embedded memories represent a significant portion of chip area. Also, the ratioof the leakage power of those memories to the leakage power of the SoC is higher and higher with thescaling of transistor size. If we can turn off the supply voltage of embedded memories without losing thedata when the system is in standby mode, the static power consumption can drastically be reduced suchthat the objective of low power consumption can be achieved. Therefore, many emerging non-volatileRAMs have been proposed to attempt to replace current flash memories and DRAMs for improving thepower consumption and performance. Resistive nonvolatile memories have been acknowledged as goodcandidates. However, how to test those RAMs using emerging devices is one big challenge.Consequently, this project is to develop comprehensive testing techniques for resistive nonvolatilememories, including fault modeling, development of test algorithms, development of built-in self-test(BIST) circuits, and platform of test algorithm generation, fault coverage evaluation, and BIST designautomation.