Testing and Reliability-Enhancement Techniques for Stacked Memories(3/3)

Project Details


Through-silicon-via based 2.5D/3D IC is one important IC design technology. However, testing andreliability issues are two key challenges for the volume production and quality of 2.5D/3D ICs.Therefore, we attempt to develop important techniques for overcoming those two issues under the grandproject entitled“Design-for-Testability and -Reliability Techniques for 2.5D/3D ICs” which includessix subprojects. Those subprojects are: subproject 1 entitled “Device and Circuit Reliability Analysis forStacked Memories”; subproject 2 entitled “Testing and Reliability-Enhancement Techniques for StackedMemories”; subproject 3 entitled “Controller-Level Reliability-Enhancement Techniques for StackedMemories”; subproject 4 entitled “Design-for-Reliability Techniques for Processor Cores of 2.5D/3DICs”; subproject 5 entitled “Test Optimization Techniques for 2.5D/3D ICs”; and subproject 6 entitled ”Design-for-Reliability Techniques for Power/Ground Networks of 2.5D/3D ICs”. We will developcircuit-level, RTL-level, and architecture-level testing and reliability-enhancement techniques for2.5D/3D ICs.Undoubtedly, stacked memory is one key component in 2.5D/3D ICs. Therefore, subproject 2 willdevelop effective testing and reliability-enhancement techniques for stacked memories in 2.5D/3D ICs.Those techniques include 1) built-in self-test techniques for stacked memories, 2) built-in self-repairtechniques for stack memory arrays, 3) built-in self-repair techniques for IO channels of stackedmemories, 4) adaptively dynamic error-correction-code scheme for stacked memories, and 5) hybridspare bits and error-correction-code techniques for stacked memories.
Effective start/end date1/08/1831/07/19


  • 2
  • 5D/3D IC
  • testing
  • reliability
  • built-in self-test
  • built-in self-repair
  • error correction code


Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.
  • Testing of in-memory-computing 8T SRAMs

    Tsai, T. L., Li, J. F., Hsu, C. L. & Sun, C. T., Oct 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc., 8875487. (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    21 Scopus citations