Synthesis and Optimization Techniques for Wdf-Based Analog Circuit Emulators(2/3)

For system verification, digital circuits can be verified by hardware emulation with Field-Programmable Logic Array (FPGA) to obtain significant simulation speedup. However, no similar emulation mechanism is available now for analog circuits to speed up the simulations. Users still have to spend a lot of SPICE simulation time on the verification for analog parts. It makes the verification of mixed-signal systems become a big bottleneck in the design flow. Therefore, in our previous project, we proposed to use the Wave Digital Filter (WDF) theorems on analog circuit emulation. Using this technique, the analog circuits can be emulated in digital environment through mapping the analog circuits with continuous signals into digital equivalent circuits with discrete signals. Because the analog circuit emulation and digital circuit emulation can be directly integrated in the same environment, the verification bottleneck of mixed-signal systems can be eliminated with this technique.In this analog emulation flow, the first step is to develop a method to automatically translate the analog circuit netlist into the corresponding WDF netlist. This step was mostly completed in our previous project. However, there is still one step to synthesize the WDF netlist into FPGA before starting circuit emulation. This hardware implementation step can be roughly divided into four parts: fixed-point transformation, synthesis and optimization of WDF structure, pipeline design and retiming, and FPGA implementation. Although there are a lot of works in the literature about FPGA synthesis and optimization, proper modifications are still required for those algorithms to generate optimal emulators because the WDF properties are different from those of traditional digital filters. Therefore, in this project, we will try to develop a series of CAD tools for the design and optimization of the synthesized WDF circuits to improve the efficiency of mixed-signal system verification. With these new techniques, this analog circuit emulation platform can certainly save considerable simulation time for analog circuits and eliminate the verification bottleneck of mixed-signal systems.