In this project, we design hardware architecture for digital signal processing in the frequency domain for synthetic aperture radar (SAR) imaging. The functional blocks include range compression, secondary range compression, azimuth compressing and range cell migration correction. The configurable hardware accelerator aims to satisfy the requirements of real-time processing.
|Effective start/end date||25/06/21 → 24/12/21|
UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This project contributes towards the following SDG(s):
- Synthetic Aperture Radar
- Architecture Design
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