Phase Shifter Chips with Low Phase and Amplitude Errors for Next-Generation Mobile Communication Systems

Mobile communications is an indispensable component in modern life. At the pace of ten years pergeneration, the mobile technology continues to progress, making our life more and more convenient.Expected to be deployed in 2020, the 5th generation (5G) mobile network will feature a larger amount of data,faster data rate, and shorter latency, and is able to support a larger number of connections with lots of mobiledevices at the same time. In next-generation mobile network, due to the increasing number and density of theconnected devices, one macro-cell base station will be replaced by multiple small-cell base stations. Toenhance the spectral efficiency, massive MIMO has been proposed as a key enabling technology for smallcell. As for RF frontend, phased array, with beam steering capability, is the most natural and straightforwardarchitecture for implementing massive MIMO for small cell in next-generation mobile communicationsystems. To realize phased arrays, phase shifters are the most essential building blocks.This project, namely, “Phase Shifter Chips with Low Phase and Amplitude Errors for Next-GenerationMobile Communication Systems,” is proposed in response to the call for proposal of the big project“Development of 5G Industrial Technology by Collaboration of Universities and Research Institutes”, whichis managed by the Ministry of Science and Technology (MOST). The purpose of the proposed project is todevelop CMOS phase shifter chips that meet the need of Industrial Technology Research Institute (ITRI).According to the specifications set by ITRI, we will design a 3.5-GHz 5-bit phase shifter with RMS phaseerror less than 4° and amplitude error less than 0.5 dB using TSMC 65-nm CMOS technology. We plan torealize this phase shifter based on vector-summing topology. The core sub-circuits in the phase shifters willbe fully differential. Transformer baluns will be used to convert the differential signals to single-end ones forthe input and the output. The variable-gain amplifiers in the vector-summing phase shifter will beimplemented using area-resizing technique. We plan to finish the proposed project in 1 year. Within theproject period, there will be two design cycles. The chip designs developed under this project will bedelivered to ITRI and used in its wireless transceivers for next-generation mobile communication systems.