Implementation of SAR Imaging Algorithm on Platform with High Bandwidth Memory

Project Details


The high bandwidth memory (HBM) inside the FPGA chip is utilized for implementing range Doppler algorithm in FPGA platform for synthetic aperture radar real-time high-resolution imaging. Through AXI bus with parallel processing, data transfer between HBM and two-dimensional FFT for range Doppler algorithm can meet the throughput requirement. Furthermore, with proper memory addressing and data allocation, we can utilize the burst access of HBM for two-dimensional FFT so that real-time processing can be realized.
Effective start/end date14/01/2213/07/22

UN Sustainable Development Goals

In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This project contributes towards the following SDG(s):

  • SDG 9 - Industry, Innovation, and Infrastructure


  • Synthetic Aperture Radar
  • Real-time Imaging
  • High Bandwidth Memory


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