Advance in integrated circuit (IC) fabrication technology facilitates the high-speed transmissionof data to be upward evolved into several gigabits per second (Gbps). The high-speed serial linktechnology is the major technique in modern data transmission. It is widely employed in wirelineSerDes applications. As the transmitted data rate has been upgraded into milti-Gbps, the signal of thedata launched by the transmitter (TX) accompanies the higher order harmonics. It results in thepower-radiated electromagnetic interference (EMI) issue and may stringently affect the other equipmentin the vicinity. Thus, an EMI-reduction power IC or a spread-spectrum clock generator (SSCG) plays animportant role in such critical building blocks. Moreover, the signal integrity (SI) has to been consideredcarefully. The higher data transmission has the more channel loss. Furthermore, a simple compensationmechanism is not suitable for various transmission channels. Thus, a continuous time linear equalizer(CTLE), a feed-forward equalizer (FFE), a decision feedback equalizer (DFE) or a clock and datarecovery (CDR) becomes a challenge and prospective work. By the EMI suppressing technology andthe good SI of high-speed data transmission, the capabilities of low-EMI, high-speed data transmissionand good power-efficient are derived.In the first year, we would implement the EMI-reduction power IC and other functional circuitsfabricated in 180 nm and 90 nm CMOS process, respectively. In the second year, we would focus on thedesign of the first year and verify the designed functions. We would extend the schemes into 40 nmCMOS process. Finally, in the third year, we would develop the integrations of TX and receiver (RX).
|Effective start/end date||1/08/18 → 31/07/19|
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