As the Big-data era is coming, algorithms of deep-learning require high accuracy of precise recognition, opening the gate to a new era of AI. Semiconductor industry is the cornerstone of technology innovation, which serves as the core of computing architecture for neuro-network and related circuitries. This project, based on this perspective and with focus on hardware development, will be targeted for the design and implementation of a more efficient, energy-saving, and low-cost devices and circuits for the further development of neuro-networks in the future AI generation. The core functionalities of a neuron-network architecture include Synapses, Neuron, and Activation function. However, these three main functionalities actually develop individually with very low integrations. Therefore, in order to realize high-performance and low power consumption, based on this goal, this project firstly raises a technology platform of FinFET Single-gate Non-volatile Memory, which integrates the core functionalities of synapse, neuron, and activation functions into one device. Moreover, one can design, implement, and prove the functions of neuromorphic computing AI chip on this platform.The operation principle of FinFET SG-NVM is to sense the varying of drain current by modulation of the channel Vth in a FinFET, whose gate electrode is connected to the bottom electrode of RRAM MIM. To apply this FinFET SG-NVM in Neuromorphic computing applications, in the first year of this project, we will design and prepare the FinFET SG-NVM device with capability of linearly tunable conductance. We will utilize the FinFET technology developed by NDL to prepare the FinFET device on the front end of line and then will grow the RRAM MIM on the metal 1 layer with a connection to the gate electrode of the prepared FinFET device. Next, in the second year, we will realize the three main operations in a FinFET SG-NVM unit cell, including (1) linearly tunable conductance(Synapse); (2) accumulation of conductance(neuron); (3) high pass filtering capability by Vth modulation of SG-NVM, imitation of ReLU activation function. Furthermore, we will fabricate a tested 1kbit NOR-type FinFET SG-NVM MACRO. In the last year, we will propose the hetero-integration solution of AI chips by the integration of FinFET SG-NVM MACRO chip and planar-CMOS periphery circuits. That is, we separately prepare FinFET SG-NVM MACRO chip in NDL and design the periphery circuitries in CIC. The latter will be manufactured in foundry. Then we can bond together both the chips on a PCB board through wiring. A hetero-integrated AI chip can be obtained thereby. Finally, we will use this AI chip in the train and inference of the handwriting English alphabet database.