Design and Implementation of Key Techniques in 56/28 Gb/S Dual-Mode High-Speed Serial Transceiver(3/3)

Project Details

Description

With the rapid growing of consumer electronics, data transmission rate has evolved to gigabits per second (Gbps) and move toward higher rate. As a key technology for mass data transmission, high-speed serial link technology has been widely used in wireline transceiver and has developed four-level pulse amplitude modulation (PAM4) data. With the rapid increase of data rate and the introduction of new data format, new issues must also be examined. First, the higher operation speed means shorter clock period and higher percentage of clock skew and jitter. At the same time, the multi-level of PAM4 data also increases the percentage of data edge in the period and severely affects the transceiver operation. Therefore, a highly accurate clock generator such as phase-locked loop (PLL) and spread-spectrum clock generator (SSCG) will play an important role in such applications. In addition, the increase in data rate also means the higher channel loss. and the multi-level of PAM4 data also compresses the data amplitude and reduces the signal integrity (SI). As a result, a single compensation mechanism is no longer sufficient. Thus, the development for key technologies of continuous time linear equalizer (CTLE), feed-forward equalizer (FFE), decision-feedback equalizer (DFE) and clock and data recovery circuit (CDR) becomes a challenge and prospective work. By ensuring the clock quality and signal integrity, the dual-mode high-speed transceiver for PAM4 data is developed. The first year will design the key circuits in high-speed serial transceiver, collect and analyze relevant literatures, verify ideas through circuit simulation and chip measurement. In the second year, the preliminary integration for transmitter and receiver will be carried out, and the key technologies of first year will be brought in to prepare for the final high-speed serial transceiver. In the third year, the key point is to optimize the integration of transmitter and receiver in serial transceiver. The system architecture and essential circuit will be adjusted based on the experience of previous year to achieve a 56/28 Gbps dual-mode high-speed serial transceiver.
StatusActive
Effective start/end date1/08/2231/07/23

Keywords

  • High-Speed Serial Link Technology
  • Low-Noise Clock Generation
  • Signal Integrity of High-Speed Data Transmission
  • Phase-Locked Loop
  • Spread-Spectrum Clock Generator
  • Continuous Time Linear Equalizer
  • Feed-Forward Equalizer
  • Decision-Feedback Equalizer
  • Clo

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